← Back
Editing: CS35L56_Rev4.5.3.wmfw
WMFW( % ; L ��=h �0 Mon 02 Jun 2025 14:12:04 Central Daylight Time $ � H � + � * � � � � � � �$ 8 � 0 � �\ 0 � 4 � � � � �� + � b � @ j �� H d� Z � 6 M � � � �� � � �� � ( �( �$ �q �)� �' �� �& R �" � �! � ) ��# � �* � ' �+ � �,� 6 B � � ( � . = �-� � 8 �. + ( �1� �0 0 � �5� �7 J : �4 � �8 ~ � �9 ~ �/ 3 �: �ޭ -\ ��� �� � � � � � � � � � $ � : | W w !O� ��`�@ � �aO� �p���P P�@� P �� ��Ht��H D� �� a����!К@�� @ � � � ���!�H�H�b�՚Ԛ@Ԛ@�H� H�P�0���@U�@�H�@�����r �H� � � \�]�\�� � � w i�lљuݙ � � t z�� � �!� P !O� n �p��@ ���� `��� �@�@� &0 � P�� n�ɐ^�> �� @����� $� � �H� O � @�@� � O�} ��� �� �@ �@` � ��@ �� � �� � @ �@ `�O� 1 �L �6 �@ � �� � AO��}n �� �@ �x6 �� � �� � � ���@���b� � �O�l � � �y��!� ��� Y)QO ���� n, �)��! �@�D� �A i@ @#) �� � � z��G�)��@���) �D��)�� ���� z hِ@��@m�X� ���c��)�A�� �@O �Oҙz��@� � �� ��z�� G�� �@�* ��� � ) � ̯a��)��D� � )�։� �O� ) �,��)**-�����a��))�a焙*�1� )ny�@ �@^ � �p�� P��O� ~R �� �@ 6 -� nx��� � i� � =�� )�Q_�QOp ,�`�� Oa_�_��;�� U�B� ��� � � 6 l �ל� �� ��O� � �@ )�� � )� %�� Ϲ����� O���A � @ � �!� � �� �y � ��� z��!�@O�6!�5p� � � @�6 � 1� n � �xO��_� ��� lй� �� / ^ �u� ) � ��r_Q �� 4)�1_�i� � O�� AV�a_�_b R�_�8 Q�I� � � ��b ��P��� ת �� �@��@%��n�$� �mf@ 0������JaJ �V�i���Ah0i V�0�� �Ah�i Vh0�� �AV�i �h0�� � ��@ 0P�0 �# � � pH'� � F� �Q0 � �P � m� P0H%�!0� F� �0 �p � ��@ !O� �PO� ʚA� a b b&�a� �� ��@� Y���� ���_� �r ���@ �� �@ �D� �� � �I/���O�I� / ���@��O�I� I� /��/� �@� �@��&�B��� ',F�@� 0�� ( � �� K������O�� � �@�'#� � ��� ! p :� � �@ :� �� :� �:��@ � ��I� ��/Q � n �@� ���� �n A '! � �` � �!� � P �C:�� � O �(6 ��L� |� � ; ;� ;P��� � P )�t�_�a_���`C� ���#A�Ӟ� 0F P &� �6 f ` 6�0 _� 2�A�� �@�`�?0� �� �� I@ )� �� '� �I�� ��O�O�� � �@q n ! �� � � d �0 � @ (V � p z� � �@ � v�O�� O؏@ !�� ��� � p � z � � �� �� N@ � �D� � �)�Oً8Q��ns� T�)O��� �@\�0 �� @ O��� ���� !��� � �� �� "��!� � !0)����F � [@�� � !� �O�� � @�4���� 0�0��� �Lٰ 8�$ٰ �4��� �L�1ظ���F !@L1�HY� � �`�d���� ���ap�d���� � ������ O��m�� ����B��@I�m �T@�Y����@� )�$%��&`�b�~ڋ_���~i�a\�n���l� ���a����#�ʅ ��s� +� ���vɁ0 � 0%Q�@����0 �%� �C� @ o�֏;� ������!0 J�@֞\� Ѫ� m��ѷ� ��#����� �O�� e�� @ 9I��K�d!� � ��FQ�S � (�@z�!i�%i 7�f������ v� w0 � (%f�!i� 7�%m�� {�l���T�Tё!aO�e x�P �%5X��' �� l� �'1��a �U � �%Q~� � �\ o�� �� �vȁ� \��֞ � ��� m�"�� i�������� eO��� D���%HP���Xȗ� � !i (o����%����v�0 ڏ@ � !i (o����%����v��@m�TO�@��!a�%e ��� � e @ �$� ��Hn�%�%� I�( ��I��� �� & ��J�� � �� �� & � ���IH� I� � %�� h.�� � �, ��U�@T��!�q�@�%���(�*� I� ��%���� �� �� I � %�� � � ��� I������ �� %h.��@ ��� �h.A Pπ�� �C��@��F�|�,����A��L��M�y�l��5�L�N������ � R 2�� �� �� �1� �%M� 9O� � �� �� �&(��X(��� ������h�r�(m%���J� �� v(@x����� a%�mx� ��(��Z�&��������h �r���%���J(m@[� v�T� �(@x���� a�%mx � � �T��EO@ ��0��Fh�m ��� ���Q���'�d}%A�$��r9�Ik�]!�% ����(h�\h m>��!m ��n�D�I����� ak%�� ��О���"�����P$�h �r���%���J(m@[� v�T� d ���i��K��� a%�OኀP�`� ��@ �q��h�m Ȝ� ��'a�)����i�%q$��yG����& i�b@ �m� ���h�h �(>��\m mn�!D�����Y�� r� '��@ �A ��& �(���� ������h�r�(m%���J�@[� v� T@x����(��x x� �h ��Q� �Ch�H8� �h �&����(�� F��F�9h�r�`m,X��X���� v(Ix��� �!emٰ ��&����(���F����9h r�Fm,X�X`@[Бv� T�x��� (Ie��َ!�m�`O��P J�q�@hm ��� � �@ �� � FIRMWARE_CS35L56 4 FW_HL_STT FIRMWARE_CS35L56_HALO_STATE < FW_HL_HARTBAT FIRMWARE_CS35L56_HALO_HEARTBEAT 4 FW_PWR_MD FIRMWARE_CS35L56_POWER_MODE � < FW_ADO_BLK_SZ FIRMWARE_CS35L56_AUDIO_BLK_SIZE � 8 FW_RFCLK_SRC FIRMWARE_CS35L56_REFCLK_SRC � D FW_PLL_RFCLK_FRQ FIRMWARE_CS35L56_PLL_REFCLK_FREQ � D FW_PLL_MCLK_FRQ%FIRMWARE_CS35L56_REFCLK_PLL_FREQ_MCLK 0 FW_I2S_EN FIRMWARE_CS35L56_I2S_EN � 8 FW_BOT_RASN FIRMWARE_CS35L56_BOOT_REASON � @ FW_REFCLK_DET "FIRMWARE_CS35L56_REFCLK_DETECT_32K � < FW_HW_CLCK_STT FIRMWARE_CS35L56_HW_CLOCK_STATE � @ FW_CP_MTR_ENBL !FIRMWARE_CS35L56_CPU_METER_ENABLE � D FW_MPS_OVRRN_FLG "FIRMWARE_CS35L56_MIPS_OVERRUN_FLAG � D FW_MIPS_OR_HBN $FIRMWARE_CS35L56_MIPS_OVERRUN_HB_NUM � � � AUDIO_SYSTEM 4 AS_ADO_STT AUDIO_SYSTEM_AUDIO_STATE � 0 AS_LST_CMD AUDIO_SYSTEM_LAST_CMD � H STRM_TO_SYNTH_DN &AUDIO_SYSTEM_STRM_ACTIVE_TO_SYNTH_DONE � H SYNTH_TO_STRM *AUDIO_SYSTEM_SYNTH_ACTIVE_TO_STREAM_ACTIVE � @ PLL_RS_REQ &AUDIO_SYSTEM_AMP_PLL_UNLOCK_RESYNC_REQ � H STRM_TO_SYNTH *AUDIO_SYSTEM_STREAM_ACTIVE_TO_SYNTH_ACTIVE � ( AS_ERRRAUDIO_SYSTEM_ERROR � 8 AS_PAK_CP_LAD AUDIO_SYSTEM_PEAK_CPU_LOAD � < AS_CRRNT_CP_LAD AUDIO_SYSTEM_CURRENT_CPU_LOAD � @ AS_SYNTHSS_ENBLD AUDIO_SYSTEM_SYNTHESIS_ENABLED � $ 4 AS_ADO_STTSAUDIO_SYSTEM_AUDIO_STATUS � % 0 AS_PRJCT_IDAUDIO_SYSTEM_PROJECT_ID & 0 AS_CHNNL_IDAUDIO_SYSTEM_CHANNEL_ID ' 8 AS_SNPSHT_ID AUDIO_SYSTEM_SNAPSHOT_ID �\ � ACTISONIC � < ACTISONIC_ENABLE ACTISONIC_ACTISONIC_ENABLE � � � CLIP_DETECT � � INPUT_CONDITIONER T IC_EN ?INPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_ENABLE � \ IC_CH_BAL AINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL � d IC_CH_BALSMHINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL_SMOOTH � h IC_MM_XO_ENMINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_MONOMIX_XOVER_ENABLE � d IC_H_XO_EN JINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE � / h IC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL � �0 � INPUT_ENHANCE \ IE_DRC_LD_OP_LVL 8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � & H IE_DRC_OP_LVL +INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � + X IE_ENABLE <INPUT_ENHANCE_INPUT_ENHANCE_CTRL_STRUCT_INPUT_ENHANCE_ENABLE � � � LIMITER T LI_DRC_LD_OP_LVL 2LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! D LI_DRC_OP_LVL %LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & D LI_ENABLE *LIMITER_LIMITER_CTRL_STRUCT_LIMITER_ENABLE � � � LOGGER $ ENABLE LOGGER_ENABLE � $ STATE LOGGER_STATE � $ COUNT LOGGER_COUNT � 8 FRMPRWIN LOGGER_FRAMESPERCAPTUREWINDOW � 4 LOGGER_VAR LOGGER_VARIABLE_VARIABLE �< @ LOGGER_VAR_TYPES LOGGER_VARIABLE_VARIABLE_TYPES � DATA LOGGER_DATA �x � � THRESHOLD_LOGGER , ENABLE THRESHOLD_LOGGER_ENABLE � 4 MAX_TEMP THRESHOLD_LOGGER_MAX_TEMP � < THRE_LOG_MAX_EXC THRESHOLD_LOGGER_MAX_EXC @ OVER_TEMP_COUNT THRESHOLD_LOGGER_OVER_TEMP_COUNT � < OVER_EXC_COUNT THRESHOLD_LOGGER_OVER_EXC_COUNT � < ABNORMAL_MUTE THRESHOLD_LOGGER_ABNORMAL_MUTE � �L � MBDRC / T M_DRC1_LD_OP_LVL 0MBDRC_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � O @ M_DRC1_OP_LVL #MBDRC_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � T T M_DRC2_LD_OP_LVL 0MBDRC_DRC_2_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � t @ M_DRC2_OP_LVL #MBDRC_DRC_2_STRUCT_DRC_OUTPUT_LEVEL � y T M_DRC3_LD_OP_LVL 0MBDRC_DRC_3_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � � @ M_DRC3_OP_LVL #MBDRC_DRC_3_STRUCT_DRC_OUTPUT_LEVEL � � D MBDRC_ENABLE $MBDRC_MBDRC_CTRL_STRUCT_MBDRC_ENABLE � � � NOISEGATE X NG_DRC_LD_OP_LVL 4NOISEGATE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! D NG_DRC_OP_LVL 'NOISEGATE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & L NG_ENABLE 2NOISEGATE_NOISE_GATE_CTRL_STRUCT_NOISE_GATE_ENABLE � � � PDL � 0 PDL_0_ENABLE PDL_PDL_0_ENABLE � 0 PDL_1_ENABLE PDL_PDL_1_ENABLE � 8 PDL_0_HI_FR PDL_PDL_0_VARS_HI_FULL_RATIO � < PDL_0_PTHRESH PDL_PDL_0_VARS_PIANO_THRESHOLD � @ PDL_0_PATTNTN PDL_PDL_0_VARS_PIANO_ATTENUATION � @ PDL_0_PBNDSIG PDL_PDL_0_VARS_PIANO_BAND_SIGNAL � 8 PDL_1_HI_FR PDL_PDL_1_VARS_HI_FULL_RATIO � < PDL_1_PTHRESH PDL_PDL_1_VARS_PIANO_THRESHOLD � @ PDL_1_PATTNTN PDL_PDL_1_VARS_PIANO_ATTENUATION � @ PDL_1_PBNDSIG PDL_PDL_1_VARS_PIANO_BAND_SIGNAL � � PICL � � PROTECT_LITE . < CAL_R_EXPECTED PROTECT_LITE_R_CALIB_0_R_REF < CAL_R_DELTA"PROTECT_LITE_R_CALIB_0_R_DELTA_MAX � LCHIRP_CUR_FREQhPROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_CURRENT_FREQUENCY | LCHIRP_FSTOP \PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_FSTOP | LCHIRP_AMP `PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_AMPLITUDE C T CALI_TUNE_APP_EN 2PROTECT_LITE_SMART_CALIBRATION_APPROVE_TUNE_ENABLE D T CALI_NORM_EN 4PROTECT_LITE_SMART_CALIBRATION_NORMALIZE_REDC_ENABLE E L CALI_TEMP_OFFSET *PROTECT_LITE_SMART_CALIBRATION_TEMP_OFFSET F T CALI_MIN_EST_TMP 3PROTECT_LITE_SMART_CALIBRATION_MIN_EST_AMBIENT_TEMP G T CALI_MAX_EST_TMP 3PROTECT_LITE_SMART_CALIBRATION_MAX_EST_AMBIENT_TEMP P PROTECT_LITE_EN2PROTECT_LITE_PROTECT_LITE_CTRL_PROTECT_LITE_ENABLE H CAL_EN 1PROTECT_LITE_PROTECT_LITE_CTRL_CALIBRATION_ENABLE H DIAG_EN1PROTECT_LITE_PROTECT_LITE_CTRL_DIAGNOSTICS_ENABLE L CAL_CHECKSUM ,PROTECT_LITE_VAR_ARRAY_CHECK_SUM_CALIBRATION � H CAL_STATUS /PROTECT_LITE_VAR_ARRAY_IMPEDANCE_MEASURE_STATUS � L CAL_R 5PROTECT_LITE_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION � P CAL_SET_STATUS 3PROTECT_LITE_VAR_ARRAY_IMPEDANCE_THRESH_CALC_STATUS L CAL_R_SELECTED -PROTECT_LITE_VAR_ARRAY_INITIAL_CALI_IMPEDANCE L TEMP_COIL_RATE /PROTECT_LITE_VAR_ARRAY_RATE_OF_COIL_TEMP_CHANGE � H TEMP_EST_COR )PROTECT_LITE_VAR_ARRAY_TEMP_EST_CORRECTED � H TEMP_COIL_C.PROTECT_LITE_VAR_ARRAY_TEMP_MEASURED_CORRECTED � L FIX_MOD_MAX_EXC.PROTECT_LITE_VAR_ARRAY_FIX_MODEL_MAX_EXCURSION � L DD_MAX_EXC 0PROTECT_LITE_VAR_ARRAY_DIRECT_DISP_MAX_EXCURSION � P OVERS_REACT_GAIN .PROTECT_LITE_VAR_ARRAY_OVERSIGHT_REACTION_GAIN � < TONE_FLAG PROTECT_LITE_VAR_ARRAY_TONE_FLAG � P MAX_EXC_BEFO_LIM /PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_BEFORE_LIMITER � T EXC_AFTER_LIM 4PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_VALUE_AFTER_LIMITER � D EXCUR_GAIN_MAX %PROTECT_LITE_VAR_ARRAY_EXCUR_GAIN_MAX � X THERM_OVER_ACT_I 4PROTECT_LITE_VAR_ARRAY_THERM_OVERRIDE_ACTIVATION_IND � P THERM_R_ATT_MIN3PROTECT_LITE_VAR_ARRAY_THERMAL_RATE_ATTENUATION_MIN � L THERM_ATTEN_MIN.PROTECT_LITE_VAR_ARRAY_THERMAL_ATTENUATION_MIN � T CB_THERM_ATT_MIN 3PROTECT_LITE_VAR_ARRAY_COMB_THERMAL_ATTENUATION_MIN � L EXC_GAIN_DIG2MM,PROTECT_LITE_VAR_ARRAY_EXCURSION_GAIN_DIG2MM � H EXC_OFFSET_MM *PROTECT_LITE_VAR_ARRAY_EXCURSION_OFFSET_MM � ( D TEMP_COIL_EST $PROTECT_LITE_VAR_ARRAY_TEMP_COIL_EST B T CAL_AMBIENT9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_AMBIENT_TEMPERATURE � C D DIAG_F0,PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F0 D X DIAG_F0_STATUS 9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_ANALYSIS_STATUS F d CAL_IMP_MEAS_CAL @PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION G D CAL_R_OUT +PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_R_OUT K T DIAG_Z_LOW_DIFF6PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_DIAGNOSTICS_LOW_DIFF L L CAL_RE_EST_GAIN-PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_RE_EST_GAIN M P CAL_ALPHA_REF 1PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_ALPHA_REFERENCE N H CAL_TC0_CALIB +PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_TC0_CALIB V P CAL_ZCURVE_F_LOW /PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F_LOW Y \ CALI_EST_AMB_TMP 9PROTECT_LITE_SMART_CALIB_VAR_ARRAY_ESTIMATED_AMBIENT_TEMP �T � VIRTUAL_SUB J 4 VS_ENBL VIRTUAL_SUB_VIRTUAL_SUB_ENABLE � �p � ULTRASONIC � P ULTRASONIC_EN 3ULTRASONIC_ULTRASONIC_CTRL_STRUCT_ULTRASONIC_ENABLE � � � MDSYNC �8 � PM < PM_TIMEOUT_TICKS PM_PM_TIMER_TIMEOUT_TICKS � , PM_CUR_STATE PM_PM_CUR_STATE 4 PM_PWR_ON_SEQ PM_POWER_ON_SEQUENCE � � 0 ACTIVE_SEQUENCEPM_ACTIVE_SEQUENCE �� � 4 STANDBY_SEQUENCE PM_STANDBY_SEQUENCE �� � � MAILBOX , QUEUE_BASE MAILBOX_QUEUE_BASE , QUEUE_LEN MAILBOX_QUEUE_LEN , QUEUE_WT MAILBOX_QUEUE_WT , QUEUE_RD MAILBOX_QUEUE_RD $ STATUS MAILBOX_STATUS � � BASS_EXTENSION , ENABLE BASS_EXTENSION_ENABLE � L B_EXT_MXSHLFGAIN *BASS_EXTENSION_BASS_EXTENSION_MAXSHELFGAIN � P BASS_EXT_GAIN 0BASS_EXTENSION_BASS_EXT_VARS_BASS_EXTENSION_GAIN � �P (� TONE_ATTENUATOR , ENABLE TONE_ATTENUATOR_ENABLE � �8 $� SDL ENABLE SDL_ENABLE � � )� WRITE_DETECT �( '� VIMON_CALIBRATION 0 ENABLE VIMON_CALIBRATION_ENABLE < VBSTMAX_VMON VIMON_CALIBRATION_VBSTMAX_VMON < VBSTMAX_IMON VIMON_CALIBRATION_VBSTMAX_IMON H VI_CAL_CL_H_DLY)VIMON_CALIBRATION_VIMON_CLASS_H_CAL_DELAY H VI_CAL_CL_D_DLY)VIMON_CALIBRATION_VIMON_CLASS_D_CAL_DELAY @ VI_CAL_CL_STT !VIMON_CALIBRATION_VIMON_CAL_STATE ( VSCVIMON_CALIBRATION_VSC ( ISCVIMON_CALIBRATION_ISC � &� SECURE_ACCESS � "� SDCA H FU21_MR_US_MU_CU 'SDCA_FU21_MAIN_RENDER_USER_MUTE_CURRENT H FU21_MR_US_MU_NE $SDCA_FU21_MAIN_RENDER_USER_MUTE_NEXT � L FU21_MR_US_VO_CU )SDCA_FU21_MAIN_RENDER_USER_VOLUME_CURRENT H FU21_MR_US_VO_NE &SDCA_FU21_MAIN_RENDER_USER_VOLUME_NEXT � D FU23_MR_PLAT_MUT #SDCA_FU23_MAIN_RENDER_PLATFORM_MUTE � 8 FU23_MR_GAIN SDCA_FU23_MAIN_RENDER_GAIN � < FU26_ULTRAS_MUTE SDCA_FU26_ULTRASONIC_MUTE � < FU26_ULTRAS_GAIN SDCA_FU26_ULTRASONIC_GAIN � % H PPU21_MA_PO_NU_C &SDCA_PPU21_MAIN_POSTURE_NUMBER_CURRENT & D PPU21_MA_PO_NU_N #SDCA_PPU21_MAIN_POSTURE_NUMBER_NEXT � 5 < SAPU29_PROT_MODE SDCA_SAPU29_PROTECTION_MODE 6 @ SAPU29_PROTEC_ST SDCA_SAPU29_PROTECTION_STATUS > < XU22_MR_BYPASS SDCA_XU22_MAIN_RENDER_BYPASS � C 4 XU22_FDL_STATUSSDCA_XU22_FDL_STATUS � D 8 XU22_FDL_SET_IND SDCA_XU22_FDL_SET_INDEX � E < XU22_FDL_HOS_REQ SDCA_XU22_FDL_HOST_REQUEST � F @ XU24_SPK_SNS_BYP SDCA_XU24_SPEAKER_SENSE_BYPASS � H @ CS21_MR_SFI'SDCA_CS21_MAIN_RENDER_SAMPLE_FREQ_INDEX � J @ CS24_SNS_SFI !SDCA_CS24_SENSE_SAMPLE_FREQ_INDEX � L D CS25_REF_SFI %SDCA_CS25_REFERENCE_SAMPLE_FREQ_INDEX � N H CS26_ULTRASO_SFI &SDCA_CS26_ULTRASONIC_SAMPLE_FREQ_INDEX � O @ PDE22_MR_REQ_PS#SDCA_PDE22_MAIN_RENDER_REQUESTED_PS � P @ PDE22_MR_ACT_PS SDCA_PDE22_MAIN_RENDER_ACTUAL_PS � Q @ PDE24_SNS_REQ_PS SDCA_PDE24_SENSE_REQUESTED_PS � R < PDE24_SNS_ACT_PS SDCA_PDE24_SENSE_ACTUAL_PS � S D PDE23_TRD_REQ_PS "SDCA_PDE23_TRANSDUCER_REQUESTED_PS � T @ PDE23_TRD_ACT_PS SDCA_PDE23_TRANSDUCER_ACTUAL_PS � W 8 TG23_TONE_DIVIDE SDCA_TG23_TONE_DIVIDER � @ XU22_FDL_MES_OFF SDCA_XU22_FDL_MESSAGE_OFFSET � � @ XU22_FDL_MES_LEN SDCA_XU22_FDL_MESSAGE_LENGTH � �@ !� PPU ( PPU_ENABLE PPU_PPU_ENABLE � � #� EVENT_LOGGER < EVLOG_HEADER EVENT_LOGGER_EVENT_LOG_HEADER � 0 EVLOG_EN EVENT_LOGGER_ENABLED � 8 BUFFER_STATUS EVENT_LOGGER_BUFFER_STATUS � @ EVLOG_ST_OFF EVENT_LOGGER_START_STREAM_OFFSET � 8 WAS_DISABLED EVENT_LOGGER_WAS_DISABLED � < EVLOG_TS_SHIFT EVENT_LOGGER_TIMESTAMP_SHIFT � �X *� ASP_MIXER 8 ASP_MIX_ENABLE ASP_MIXER_ASP_MIX_ENABLE � � +� AUDIO_WAVETABLE � ,� BOOSTEMP H bt_en 2BOOSTEMP_BOOSTEMP_CTRL_STRUCT_FIRMWARE_BOOSTEMP_EN � 4 8 bt_rspk"BOOSTEMP_BOOSTEMP_CTRL_STRUCT_RSPK � 5 H bt_temp_est,BOOSTEMP_BOOSTEMP_CTRL_STRUCT_BOOST_TEMP_EST � �\ B SHORT_DETECT 8 SHORT_DETECTED SHORT_DETECT_SHORT_DETECTED � � � EVENT_HANDLER � � GPIO � -� AUTO_CALIBRATION � AC_SGS_THRESH sAUTO_CALIBRATION_PICL_RESISTANCE_CALIBRATION_RX_CMPST_0_Z_MEASURE_PILOT_TONE_CMPST_0_SINEGENERATORSENSE_0_THRESHOLD � T AC_R1 <AUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_0_R_REF � ` AC_R1_DELTA_MAXBAUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_0_R_DELTA_MAX � T AC_R2 <AUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_1_R_REF � ` AC_R2_DELTA_MAXBAUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_1_R_DELTA_MAX � � AC_AIIR_VAL_THRcAUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_ADAPTIVE_IIR_ORD1_CMPST_0_ADAPTIVE_IIR_ORD1_0_VALIDTHR � T AC_A0 <AUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_2_R_REF � ` AC_A0_DELTA_MAXBAUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_2_R_DELTA_MAX � T AC_RDC <AUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_3_R_REF � d AC_RDC_DELTA_MAX BAUTO_CALIBRATION_AUTO_CALIBRATION_TX_CMPST_0_R_CALIB_3_R_DELTA_MAX � \ AC_VI_SF_RATIO =AUTO_CALIBRATION_REDC_CORRECTION_0_VIMON_SCALING_FACTOR_RATIO �X .� ANALOG_CLIP_DETECT 0 ENABLE ANALOG_CLIP_DETECT_ENABLE � � 1� TWEETER_XOVER �8 0� TWEETER_LIMITER \ TLI_DRC_LD_OP_LV :TWEETER_LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! L TLI_DRC_OP_LVL -TWEETER_LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & \ TLI_ENABLE BTWEETER_LIMITER_TWEETER_LIMITER_CTRL_STRUCT_TWEETER_LIMITER_ENABLE � � 5� TWEETER_ENHANCE �< 7� SWDE H ( SWDE_ENSWDE_SWDE_ENABLE , SWDE_SW_EN SWDE_SWDE_SW_ENABLE , SWDE_DE_EN SWDE_SWDE_DE_ENABLE 8 SWDE_SW_M_F1_B0SWDE_ST_WIDE_MID_FILT_1_B0 8 SWDE_SW_M_F1_B1SWDE_ST_WIDE_MID_FILT_1_B1 8 SWDE_SW_M_F1_B2SWDE_ST_WIDE_MID_FILT_1_B2 < SWDE_SW_M_F1_MA1 SWDE_ST_WIDE_MID_FILT_1_MA1 < SWDE_SW_M_F1_MA2 SWDE_ST_WIDE_MID_FILT_1_MA2 8 SWDE_SW_M_F2_B0SWDE_ST_WIDE_MID_FILT_2_B0 8 SWDE_SW_M_F2_B1SWDE_ST_WIDE_MID_FILT_2_B1 8 SWDE_SW_M_F2_B2SWDE_ST_WIDE_MID_FILT_2_B2 < SWDE_SW_M_F2_MA1 SWDE_ST_WIDE_MID_FILT_2_MA1 < SWDE_SW_M_F2_MA2 SWDE_ST_WIDE_MID_FILT_2_MA2 8 SWDE_SW_M_F3_B0SWDE_ST_WIDE_MID_FILT_3_B0 8 SWDE_SW_M_F3_B1SWDE_ST_WIDE_MID_FILT_3_B1 8 SWDE_SW_M_F3_B2SWDE_ST_WIDE_MID_FILT_3_B2 < SWDE_SW_M_F3_MA1 SWDE_ST_WIDE_MID_FILT_3_MA1 < SWDE_SW_M_F3_MA2 SWDE_ST_WIDE_MID_FILT_3_MA2 8 SWDE_SW_S_F1_B0SWDE_ST_WIDE_SIDE_FILT_1_B0 8 SWDE_SW_S_F1_B1SWDE_ST_WIDE_SIDE_FILT_1_B1 8 SWDE_SW_S_F1_B2SWDE_ST_WIDE_SIDE_FILT_1_B2 @ SWDE_SW_S_F1_MA1 SWDE_ST_WIDE_SIDE_FILT_1_MA1 @ SWDE_SW_S_F1_MA2 SWDE_ST_WIDE_SIDE_FILT_1_MA2 8 SWDE_SW_S_F2_B0SWDE_ST_WIDE_SIDE_FILT_2_B0 8 SWDE_SW_S_F2_B1SWDE_ST_WIDE_SIDE_FILT_2_B1 8 SWDE_SW_S_F2_B2SWDE_ST_WIDE_SIDE_FILT_2_B2 @ SWDE_SW_S_F2_MA1 SWDE_ST_WIDE_SIDE_FILT_2_MA1 @ SWDE_SW_S_F2_MA2 SWDE_ST_WIDE_SIDE_FILT_2_MA2 8 SWDE_SW_S_F3_B0SWDE_ST_WIDE_SIDE_FILT_3_B0 8 SWDE_SW_S_F3_B1SWDE_ST_WIDE_SIDE_FILT_3_B1 8 SWDE_SW_S_F3_B2SWDE_ST_WIDE_SIDE_FILT_3_B2 @ SWDE_SW_S_F3_MA1 SWDE_ST_WIDE_SIDE_FILT_3_MA1 @ SWDE_SW_S_F3_MA2 SWDE_ST_WIDE_SIDE_FILT_3_MA2 ! 4 SWDE_SW_M_SCALESWDE_ST_WIDE_MID_SCALE " 4 SWDE_SW_M_SHIFTSWDE_ST_WIDE_MID_SHIFT # 4 SWDE_SW_S_SCALESWDE_ST_WIDE_SIDE_SCALE $ 4 SWDE_SW_S_SHIFTSWDE_ST_WIDE_SIDE_SHIFT % 8 SWDE_DE_M_F1_B0SWDE_D_ENH_MID_FILT_1_B0 & 8 SWDE_DE_M_F1_B1SWDE_D_ENH_MID_FILT_1_B1 ' 8 SWDE_DE_M_F1_B2SWDE_D_ENH_MID_FILT_1_B2 ( < SWDE_DE_M_F1_MA1 SWDE_D_ENH_MID_FILT_1_MA1 ) < SWDE_DE_M_F1_MA2 SWDE_D_ENH_MID_FILT_1_MA2 * 8 SWDE_DE_M_F2_B0SWDE_D_ENH_MID_FILT_2_B0 + 8 SWDE_DE_M_F2_B1SWDE_D_ENH_MID_FILT_2_B1 , 8 SWDE_DE_M_F2_B2SWDE_D_ENH_MID_FILT_2_B2 - < SWDE_DE_M_F2_MA1 SWDE_D_ENH_MID_FILT_2_MA1 . < SWDE_DE_M_F2_MA2 SWDE_D_ENH_MID_FILT_2_MA2 / 8 SWDE_DE_M_F3_B0SWDE_D_ENH_MID_FILT_3_B0 0 8 SWDE_DE_M_F3_B1SWDE_D_ENH_MID_FILT_3_B1 1 8 SWDE_DE_M_F3_B2SWDE_D_ENH_MID_FILT_3_B2 2 < SWDE_DE_M_F3_MA1 SWDE_D_ENH_MID_FILT_3_MA1 3 < SWDE_DE_M_F3_MA2 SWDE_D_ENH_MID_FILT_3_MA2 4 8 SWDE_DE_S_F1_B0SWDE_D_ENH_SIDE_FILT_1_B0 5 8 SWDE_DE_S_F1_B1SWDE_D_ENH_SIDE_FILT_1_B1 6 8 SWDE_DE_S_F1_B2SWDE_D_ENH_SIDE_FILT_1_B2 7 < SWDE_DE_S_F1_MA1 SWDE_D_ENH_SIDE_FILT_1_MA1 8 < SWDE_DE_S_F1_MA2 SWDE_D_ENH_SIDE_FILT_1_MA2 9 8 SWDE_DE_S_F2_B0SWDE_D_ENH_SIDE_FILT_2_B0 : 8 SWDE_DE_S_F2_B1SWDE_D_ENH_SIDE_FILT_2_B1 ; 8 SWDE_DE_S_F2_B2SWDE_D_ENH_SIDE_FILT_2_B2 < < SWDE_DE_S_F2_MA1 SWDE_D_ENH_SIDE_FILT_2_MA1 = < SWDE_DE_S_F2_MA2 SWDE_D_ENH_SIDE_FILT_2_MA2 > 8 SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0 ? 8 SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1 @ 8 SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2 A < SWDE_DE_S_v3_MA1 SWDE_D_ENH_SIDE_FILT_3_MA1 B < SWDE_DE_S_F3_MA2 SWDE_D_ENH_SIDE_FILT_3_MA2 C 4 SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALE D 4 SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFT E 4 SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALE F 4 SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFT I 0 SWDE_XFADE_BAL SWDE_SWDE_BALANCE � 4� BOOT_BEEP < BOOT_BEEP_ENABLE BOOT_BEEP_BOOT_BEEP_ENABLE � 4 DSP_BEEP_FREQ BOOT_BEEP_DSP_BEEP_FREQ � 8 DSP_BEEP_LEVEL BOOT_BEEP_DSP_BEEP_LEVEL � 8 bb_dsp_beep_durBOOT_BEEP_DSP_BEEP_DURATION � 4 GPI_BEEP_FREQ BOOT_BEEP_GPI_BEEP_FREQ � 8 GPI_BEEP_LEVEL BOOT_BEEP_GPI_BEEP_LEVEL � 8 bb_gpi_beep_durBOOT_BEEP_GPI_BEEP_DURATION � 4 BEEP_PENDING BOOT_BEEP_BEEP_PENDING � �h 8� PEQ20_1 L PEQ20_1_ENABLE ,PEQ20_1_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE � �h 9� PEQ20_2 L PEQ20_2_ENABLE ,PEQ20_2_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE � � /� SHARED_PATCHING_STRUCTURE P SPTCH_MD_SLW_FRM -SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES
Save File
Cancel